1. Technical Field
This invention relates to systems for generating integrated circuit mask artwork, and particularly to systems of this type which are technology independent.
2. Discussion
The digital computing revolution has, to a large measure, been driven by advances in semi-conductor technology. In particular, the availability of inexpensive, but powerful, integrated circuits has made it possible to bring computing power to the fingertips of the masses. Since the materials of which integrated circuits are constructed, (primarily silicon) are relatively inexpensive, and manufacturing processes are highly automated, design and development costs comprise a large part of their total cost. In response, a number of automated systems have been developed to facilitate the integrated circuit design process.
For example, once an electrical schematic is designed defining the required electrical components and their interconnections, much effort goes into the process of determining how to arrange the individual components and their interconnections so that they could be constructed using integrated circuit manufacturing techniques. At the high densities of today's integrated circuits sometimes a million devices may be placed on a single chip. Current manufacturing techniques involve the generation of mask artwork from the schematic. These masks are then used in the photo lithographic process involving successive layers of semi-conductor material to construct the integrated circuit.
In order to facilitate mask artwork generation a number of products have been developed which automate various stages of artwork generation. For example, a commonly used interactive computer program for device level artwork generation is known as a polygon editor, such as the system sold at one time by the Calma Company. However, the polygon editor still required manual placement and interconnection of components. Placement relationships between components Were either communicated between the schematic author and draftsman or the program relied upon the knowledge and experience of the draftsman. Unfortunately, this form of editing is tedious, slow and error prone. With a polygon editor devices are entered one layer at a time and it is up to the user to make sure that design rules are not violated. While software has been developed to assist in catching such errors these errors must be manually corrected in an iterative process that is very slow.
Another form of automated artwork generation programs are called cell level automated routing programs. These programs work with circuits made of previously generated subcircuits, or cells, and they route interconnections between cells based on the number of interconnections and the physical dimensions of the component cells. They are used typically on very large scale integration (VLSI) digital circuits which consist of previously edited cells of logic gates which are fixed.
However, very serious constraints are placed on the designer with cell level automated routing. For example, all pins or routing points must be on a grid. Also, a metal interconnect cannot run through the middle of a cell because it might hit some metal that is inside the cell since the system does not have any knowledge of where metal may be inside the cell. Cell level automated routing works well for technology like logic circuits where the performance is not critical and where there are very stable fixed components. However, these programs have no provision for routing device (transistor, resistor, capacitor) level circuits and have no mechanism for relating devices with others for placement.
As a consequence, while digital logic circuits can benefit by cell level automated routing programs, such programs could not be used for integrated circuits such as high performance digital and linear circuits, where the predetermined cells cannot be used and individual device level circuits must be routed and related to each other. This is because the physical relationships between individual devices can determine critical parameters including offset, accuracy, and in some cases, speed. That is, in digital circuits parameters such as offset do not exist since the circuits generate either one or zero states.
In contrast, in analog circuits the accuracy of the value of a signal that a circuit produces with respect to a specified value is important, and is radically affected by many factors such as the matching of components. Matching of components refers to how closely the components are manufactured in terms of their parameters. For example, the parasitic capacitance of a particular component may be one of the parameters that affects the circuit performance and, in an analog or high speed circuit, the circuit designer may be trying to match the parasitics of two devices so that they are as similar as possible since they cannot be controlled otherwise. One way to achieve this is to put the devices as close to each other on the circuit because, due to normal processing variations there are gradients running across the chip. That is, the thickness of layers will vary slightly across the chip. For this reason, for closely spaced components, the variation will be very small but if these components were widely spaced the variation could be significant.
In other cases, it may be desired to have these effects between two components cancel each other out. In such cases these devices may be placed in a mirroring orientation to provide cancelling. In addition to the effect of thickness gradients across the chip, skew between the different mask layers when the components are generated may introduce other effects. In such cases, the orientation of the device might change the parameters of the device necessitating mirroring or matching as the case may be.
For these reasons, linear and high speed bipolar digital (e.g. ECL) designers are forced to use polygon editors to design integrated circuit mask artwork, with the inherent slowness and errors inherent in this process. One exception is a group of programs known as silicon compilers, or cell synthesizers. Some of these programs have the ability to produce linear circuits with intelligent component level placement. For example, see L. R. Carley, et al., "ACACIA: The CMU Analog Design System" IEEE 1989 Custom Integrated Circuits Conference, as well as the product, "AUTO-LINEAR" sold by Silicon Compiler Systems Corporation. However, these silicon compilers suffer from two serious limitations. First, they are specifically designed for linear CMOS integrated circuit processes, a small subset of the process technologies available. Second, they do not allow arbitrary annotation of relationships between devices. That is, these programs require the user either to select a known circuit topology (with known layout constraints) or to group related components into subcells with known layout constraints (i.e., differential pairs, etc.). These limitations effectively prevent the use of these silicon compilers for state of the art circuit designs which do not conform to past circuit topologies.
Thus, it would be desirable to have a system which facilitates the generation of integrated circuit mask artwork and permits the designer to relate devices on a component level, without requiring extensive manual input. Further, it is desirable to have a system for automating integrated circuit mask artwork generation which is useful for high performance digital and linear circuits. In addition, it would be desirable to have such a system that reduces the time required for developing integrated circuit mask artwork for high performance digital and linear integrated circuits which is independent of device technology and circuit topology.